Job description
Senior / Staff / Principal Power Intent Implementation Engineer
Salary: Up to £130,000 D.O.E. + Shares
Location: Cambridge
Working Environment: Hybrid (2 days on-site)
The company is one of the most prestigious tech firms in the world and a global powerhouse in the semiconductor industry, operating at the bleeding edge of technology and redefining the way we interact with our devices through the creation of advanced semiconductor and software designs.
Following continued growth, the business is looking for a Power Intent Implementation Engineer to join their Solutions Engineering team and keeping an open mind towards their level of seniority.
As a Power Intent Implementation Engineer, you will contribute towards the development and verification of power intent for system level designs and SoC’s, collaborating closely with chip partners to support their physical implementation success. You will also be involved in the development and deployment of new methodologies to improve implementation efficiency and results, converting R&D concepts into real solutions!
Key Requirements:
Desired, but not essential:
Salary: Up to £130,000 D.O.E. + Shares
Location: Cambridge
Working Environment: Hybrid (2 days on-site)
The company is one of the most prestigious tech firms in the world and a global powerhouse in the semiconductor industry, operating at the bleeding edge of technology and redefining the way we interact with our devices through the creation of advanced semiconductor and software designs.
Following continued growth, the business is looking for a Power Intent Implementation Engineer to join their Solutions Engineering team and keeping an open mind towards their level of seniority.
As a Power Intent Implementation Engineer, you will contribute towards the development and verification of power intent for system level designs and SoC’s, collaborating closely with chip partners to support their physical implementation success. You will also be involved in the development and deployment of new methodologies to improve implementation efficiency and results, converting R&D concepts into real solutions!
Key Requirements:
- Strong understanding of power management techniques and low-power design methodologies
- Proficiency in writing and verifying UPF (Unified Power Format) to work with industry-standard EDA tools (e.g. Synopsys, Cadence, Siemens)
- Experience with low power design techniques, such as clock and power gating, voltage / frequency scaling, retention…
Desired, but not essential:
- Knowledge of microprocessor architecture
- Previous experience with programming languages for data processing and presentation - along the lines of Python, R, Go, MATLAB
- Experience with RTL design in an HDL such as Verilog, SystemVerilog or VHDL