Job description
Mid / Senior FPGA Engineer
Salary: Up to £80,000
Location: Cambridge
Working Environment: Hybrid (2 days on-site)
The company is one of the most prestigious tech firms in the world and a global powerhouse in the semiconductor industry, operating at the bleeding edge of technology and redefining the way we interact with our devices through the creation of advanced semiconductor and software designs.
Following continued growth, the business has multiple openings for Mid-level and Senior FPGA Engineers to join their FPGA Design Team within the Solutions Engineering Group.
The team’s focus is that of delivering ASIC prototypes on FPGA platforms, based around leading CPU and system IP solutions, to be used for software development and IP validation purposes both internally and by external customers.
As an FPGA Engineer, you will work on the design and implementation of these FPGA prototypes using techniques such as gated clock conversion and synthesizable models to build accurate representations of real-world systems.
Key Requirements:
Desired, but not essential:
Salary: Up to £80,000
Location: Cambridge
Working Environment: Hybrid (2 days on-site)
The company is one of the most prestigious tech firms in the world and a global powerhouse in the semiconductor industry, operating at the bleeding edge of technology and redefining the way we interact with our devices through the creation of advanced semiconductor and software designs.
Following continued growth, the business has multiple openings for Mid-level and Senior FPGA Engineers to join their FPGA Design Team within the Solutions Engineering Group.
The team’s focus is that of delivering ASIC prototypes on FPGA platforms, based around leading CPU and system IP solutions, to be used for software development and IP validation purposes both internally and by external customers.
As an FPGA Engineer, you will work on the design and implementation of these FPGA prototypes using techniques such as gated clock conversion and synthesizable models to build accurate representations of real-world systems.
Key Requirements:
- Experience working across the entire FPGA design cycle, from RTL design through to timing closure.
- Experience programming in Verilog, System Verilog or VHDL.
Desired, but not essential:
- Experience with scripting languages such as Python, TCL or similar.
- Experience or knowledge of ASIC/SoC prototyping in FPGA.
- Experience with the latest Xilinx UltraScale+ devices and tools.
- Experience or knowledge of implementation of DDR memory sub-systems.